1. Field of the Invention
The present invention relates to the fabrication of monolithic photodetectors or image sensors intended for being used in image pick up devices such as, for example, cameras, camcorders, digital microscopes, or digital photographic cameras. More specifically, the present invention relates to image sensors based on semiconductors including a single storage and photodetection element.
2. Discussion of the Related Art
FIG. 1 illustrates the simplified diagram of such an image sensor. Those skilled in the art should understand that a real device includes a plurality or array of such sensors. An elementary sensor includes, interconnected in series between a high supply rail Vdd and a low reference or ground supply rail GND, an N-channel MOS precharge transistor M1 and a photodiode D. I designates the junction node of photodiode D and of precharge transistor M1.
The sensor also includes two N-channel MOS transistors M2 and M3, in series between high power supply Vdd and an input terminal P of an electronic data processing circuit (not shown). M2 designates hereafter that of the two transistors having a source/drain terminal connected to high supply Vdd. Transistor M3, having a terminal connected to terminal P, forms a read transistor. The gate of transistor M2 is connected to node I. The gate of precharge transistor M1 can receive a precharge signal Rs. The gate of read transistor M3 can receive a read control signal Rd.
FIGS. 2A, 2B, and 2C illustrate, by timing diagrams, the variation along time, respectively, of precharge control signal Rs, of read control signal Rd, and of the voltage level of node I.
It will be considered hereafter that transistors M1 and M3 are on when their gate signal is high (1) and that they are off when this signal is low (0).
An operating cycle of the sensor starts with maintaining in the off state read transistor M3, as illustrated by the low state (0) of read signal Rd in FIG. 2B. Conversely, precharge transistor M1 is on, as indicated by the high state (1) of precharge signal Rs in FIG. 2A. In this state, node I charges to a maximum voltage Vmax which substantially corresponds to value Vdd of the high power supply.
A time t1 at which the precharge state is reached on node I is considered. The precharge control signal is then brought down to its low level, and precharge transistor M1 turns off. From this time t1, node I discharges more or less rapidly according to the lighting of photodiode D.
At a time t2, while precharge transistor M1 is still off, a reading of the cell state is performed by briefly turning on read transistor M3. For this purpose, as illustrated in FIG. 2B, a read signal Rd in the high state is applied on its gate for a short time interval xcex4t centered on time t2. The output level transmitted on terminal P depends on the charge state of the gate of transistor M2, that is, on the voltage at node I and thus on the charge stored at this node. Output P is applied to the input of an electronic processing circuit which provides an indication of the lighting of photodiode D between times t1 and t2.
FIG. 3 illustrates, in a partial simplified cross-section view, a monolithic forming of the assembly of a photodiode D and of precharge transistor M1 of FIG. 1. These elements are formed in a semiconductor substrate 1 of a first conductivity type, for example, of type P, which is lightly doped (Pxe2x88x92). This substrate for example corresponds to an epitaxial layer on a P-type silicon wafer (not shown). The active area is delimited by field insulating layers 2, for example made of silicon oxide (SiO2), and corresponds either to a portion of substrate 1, or to a well 3 of the same conductivity type as underlying substrate 1, but more heavily doped. Above the surface of well 3 is formed an insulated gate structure 4 possibly provided with lateral spacers 5. On either side of gate 4, at the surface of well 3, are located heavily-doped source and drain regions 6 and 7 of the opposite conductivity type, for example, N (N+). Source region 6 is formed on a much larger surface area than drain region 7 and forms with underlying substrate 3 the junction of photodiode D. Gate 4, source 6, and drain 7 are integral with metallizations (not shown) that make contact between these regions and precharge control signal Rs, the gate of transistor M2 (node I), and high power supply Vdd, respectively. The structure is generally completed by a heavily-doped P-type region (not shown), which enables connecting, to the reference or ground voltage, substrate 1 and well 3.
FIG. 4 illustrates in full lines the voltage levels of the various regions of FIG. 3 just after the precharge: regions 6 and 7 are at the precharge voltage, well 3 is grounded. Voltage VR of region 6 just before a reading while photons have irradiated this region has been shown in dotted lines. The precharge voltage depends on the biasing of precharge transistor M1, that is, on the level of signal Rs applied on its gate. If transistor M1 is in ohmic operation (very high Rs), regions 6 and 7 are precharged to voltage Vdd. If transistor M1 is in low-inversion operation, the voltages of regions 6 and 7 align on the level of the channel of transistor M1.
A disadvantage of this type of structure is that the maximum voltage of region 6 after the precharge is poorly defined. Indeed, a precharge noise signal having a voltage value given by relation V=kTC, where k is the Boltzman constant, T is temperature, and C is the capacitance of this diode, corresponds to the diode capacitance. This noise must be taken into account by the electronic processing circuit upon evaluation of the output state. Indeed, to be able to determine the voltage decrease due to an irradiation, the value at time t2 (FIG. 2) must be compared to the maximum precharge value. This precharge level being unknown, correlated double-sampling methods which require sampling the maximum value at the end of the precharge have to be implemented. More complex electronic systems must be provided to be able to perform a sampling at the end of the precharge. The data thus obtained must also be stored. It is then necessary to have an additional memory of same size as the total array of the image pick up device, which results in a significant bulk which limits the device miniaturization. Further, the associated electronic processings are relatively long.
The present invention thus aims at providing a novel elementary cell which enables reducing the processing time.
The present invention also aims at providing such a cell which enables reducing the bulk.
To achieve these and other objects, the present invention provides a photodetector made in monolithic form, of the type including a photodiode, a precharge MOS transistor, a control MOS transistor, and a read MOS transistor, the photodiode and the precharge transistor being formed in a same substrate of a first conductivity type, the photodiode including a first region of the second conductivity type formed under a second region of the first conductivity type, more heavily doped than the substrate, and under a third region of the second conductivity type, more heavily doped than the first region, the second and third regions being separate, the first region forming the source region of the second conductivity type of the precharge MOS transistor, the second and third regions being connected, respectively, to a fixed voltage and to the gate of the control transistor.
According to an embodiment of the present invention, the photodetector further includes a well of the first conductivity type, more heavily doped than the substrate, in which the first region is formed.
According to an embodiment of the present invention, the first conductivity type is type P and the second conductivity type is type N.
According to an embodiment of the present invention, the substrate, the well, and the second region are maintained at a low reference voltage of the circuit.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.